Some types of field effect transistors (FETs) have three-dimensional, non-planar configurations including fin-like structures extending above semiconductor substrates. Such field effect transistors are referred to as FinFETs. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.
Both nFETs and pFETs can be formed on the same substrate. Silicon channels can be employed for both types of devices. Hybrid channel FinFETs are characterized by the use of silicon channels in the nFET regions and silicon germanium channels in the pFET regions. Impurities can be introduced below the fins to provide a punch through stop (PTS). Punch through isolation of fins in a bulk FinFET device is provided to avoid leakage and is typically formed with the well implant. Ion implantation into strained semiconductors will relax them. A deeper implant is required for relatively tall fins.